processor n. 1.〔美国〕农产品加工者;进行初步分类的人。 2.(数据等的)分理者;【自动化】信息处理机。
core CORE =Congress of Racial Equality 〔美国〕争取种族平等大会。 n. 1.果心。 2.(事物、问题等的)中心,核心;精髓。 3.(地球的)地核;【地质学;地理学】岩心;【铸】型心;【建筑】衬心;【电学】(线)心,心线;(计算机的)磁心;(原子反应堆的)堆芯,活性区;(燃料元件)芯体。 4.(羊内脏中的)种瘤。 5.〔美国〕(各专业学生共修的)基础课。 throw away the apple because of the core 因噎废食。 to the core 到心,彻底(rotten to the core 透心腐烂;坏入骨髓,糟糕透顶。 English to the core道地的英国人)。 vt. 挖去…的果心。
Sprs give status and control of resources within the processor core spr给出处理器核心内部资源的状态并对其进行控制。
There are differences of opinions obviously, but i recommend you look at processor cores when comparing performance results across solutions 建议在比较解决方案的性能结果时查看处理器核心。
Using this processor core, most of complex related calculation and control function can be fulfilled by updating the software 利用它可以通过灵活的配置软件完成基带处理中绝大部分的复数相关运算和控制功能。
This processor core is of small area and very low power and can be used in programmable baseband processor design 经实际流片测试,该处理器核具有面积小、功耗低的特点,可用于多模无线通信基带处理器的设计。
This means that the kernel will detect the number of processors or processor cores and will automatically deactivate smp on uniprocessor systems 也就是内核可以侦测处理器的数量或者处理器核心数,并在单内核系统上自动关闭smp的功能。
Dual-core refers to a chip design and fabrication capability that results in two processor cores per physical chip some people go so far as to call it an smp chip 双核心是指一种芯片设计和制造能力,它可以使两个处理器核心共存于一个物理芯片中(有人甚至将其称为smp芯片)。
It focuses on the system architecture and hardware realization of the gigabit ethernet switch we designed, which include the control module with mpc8241 embedded processor core and the switch module 重点介绍了mpc8241嵌入式处理器为核心的管理模块以及交换模块的系统结构和硬件实现。
In this paper, an embedded 16-bit processor core is designed, based on the characteristics of the wireless communication algorithm and instruction level acceleration technology 文章结合无线通信处理算法的特点,利用指令级加速技术,设计了一种基于无线通信中复数运算的16位嵌入式处理器核。
The memory barrier performance of a single intel p4 with hyperthreading two processor cores on one die is faster than with two p4s, and both have different performance characteristics than sparc 一个超线程(一个模具上有两个处理器核心)intelp4的内存壁垒性能(memorybarrierperformance)要快于两个p4,而两者的性能特征又不同于sparc。
A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on-chip memories usually provides a good solution 基于总线互连的由一个或多个指令集处理器核、一个或多个专用硬件ip核、一片或多片片上存储器构成的异质体系结构成为媒体系统芯片的合理选择。